1. Field of the Invention
The present invention is related to cache memories, and more particularly to global command processing for a tiled cache memory wherein the tiles contain caches.
2. Description of Related Art
Traditional cache memory controllers feature several high-level “global” command operations that provide improved system operation and provide correctness in some multi-processor and/or multi-threading environments. Commands such as zeroing (or other initializer) operations provide a fast way to initialize data areas for programs, rather than initializing a region in memory and then having to wait for the initialized values to be loaded as the cache misses on an access to the region. Other commands such as flush and reconcile provide the ability to quickly unload a cache or a portion of a cache to ensure memory consistency.
The above operations are necessary, and where they can be implemented in a single global cache instruction, rather than having a processor perform all of the action, such global cache instructions are very useful. However, in architectures such as tiled caches, the penalty to process such an instruction in the pipeline might take as long as using individual accesses to accomplish the same task. Further, when performing a global cache operation, processing can be stalled while the operation completes.
Therefore, it is desirable to provide global commands and global command processing in a pipelined cache in such a way to efficiently perform the command operations. It would also be desirable to provide a mechanism by which slowing or halting of processing can be avoided while performing global cache operations in a pipelined cache.